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Senior IC Layout Engineer
•13 days ago
| Hours | Full-time, Part-time |
|---|---|
| Location | Austin, Texas |
About this job
DescriptionKforce has a client in Austin, TX that is seeking a Senior IC Layout Engineer who will work closely with circuit designers to generate topological layouts of high-performance, cutting-edge semiconductor products.Responsibilities:* Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies* Use problem solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications while meeting FinFET technology rules* Run physical design verification tools to debug, improve, and verify layout blocks* Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologiesRequirements* Associate or higher degree in Electronic/IC layout CAD specialization or related program* 5+ years of experience in IC layout design in FinFET technology node* Strong understanding of layout fundamentals and best practices* Solid understanding of semiconductor manufacturing process and DFM techniques* Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre* Proficient at debugging/fixing LVS/DRC errors* Must be familiar with Cadence Design Environment (CDE) and Unix OS* Must have strong communication skills and be a team player* Unquestionable ethics - treats people with respect; keeps commitments; inspires the trust of others; works with integrity* Commitment to our core values of Leadership, Innovation, Communication, Persistence, Enthusiasm, and Respect* Experience with synthesis/advanced place & route tools (Innovus) is a plus* Programming knowledge in SKILL is a plusJob TypeDirect HireCompensation140000 - $180000
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