Silicon Physical Design Engineer III

Job Title: Silicon Physical Design Engineer III Location: Sunnyvale, CA Anywhere in The USA – Remote Type: : 9 Months; Potential for extension to 6 months depends on the project schedule and resource requirement # of Openings: 1 Job Description: Top non-negotiable skill sets required for this role • Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies • Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge. • Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre Duties: • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes. • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Skills Must Have: • 5 years of relevant physical design experience • Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs • Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. • Experience in Block-level and Full-chip floor-planning, power grid planning • Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques. • Experience with Python, TCL, Perl programming Wish List/ Nice to Have: • MSEE/CS or equivalent experience Education • Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science • Master's Degree preferred but not required