Elect Design and Analy Engr 3

Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results. Requirements: Must have min Bachelor’s in engineering (no exception, please do not submit candidates without) Must have min 5 years of experience, please do not submit without, manager will reject (he’s interviews are thorough and so is his resume review, please thorough screen candidates). UVM experience is important and required. 5+ years of experience. 1-2 years of UVM tool. Cadence Xcelium verification tool. As an equal opportunity employer, ICONMA provides an employment environment that supports and encourages the abilities of all persons without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. San Naresh Phone: (248) 849-0609