Technical Leader, STA Engineer

Who We Are

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed

Who you'll work with

Our creative and talented team as Static Timing Analysis(STA) Lead in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving them to refine their design and timing constraints for physical design closure. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the backend timing signoff process including CDC checks, static timing verification, and silicon debug activities.

What you'll do

• Responsible for closing timing at block, sub-chip, and full-chip level. The tasks will include setup, hold, transition, max_cap, min_period, min_pulse_width, xtalk, noise, double switching, skew, and other timing quality checks and ECO
• You may also be involved in extraction and STA flow development/automation, convergence strategies/methodologies, correlation Place and route (PNR) to STA, Spice to STA, silicon to STA, constraints, margining, corner selection, and advising the Physical Design team on implementation best practices.
• As member of physical/implementation design team, drive methodologies and "best known methods" to streamline physical design STA work, come up with guidelines and checklists, drive execution, and track progress.
• Resolve design and flow issues related to STA, identify potential solutions and drive execution.

Who you are

You are a HW engineer with 10+ years of related work experience with a broad mix of technologies.

Minimum qualifications

• All aspects of ASIC Bachelor's or a Master's Degree in Electrical or Computer Engineering
• Integration for STA including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
• Experience on integrating IP constraints from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
• Proven experience in developing full chip timing constraints and signing off timing on complex hierarchical chips in advanced process nodes
• Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5 nm technologies.
• Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates

Preferred skills

• Synthesis Tools: Synopsys DC/DCG/FC
• Formal Verification : Synopsys Formality and Cadence LEC
• Parasitic Extraction : Synopsys Star-RCXT, Cadence Quantus
• Static Timing Verification & ECO : Synopsys Primetime/PTPX/Tweaker, Cadence Tempus
• Scripting: TCL, Perl is required; Python is a plus

Why Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we're "old" (36 years strong) and only about hardware, but we're also a software company. And a security company.

We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can't put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.

Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don't care. Tattoos? Show off your ink. Like polka dots? That's cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!

#LI-JM6